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IP Products |
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Copyright 2012, Inomize , LTD. All rights reserved. |
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Inomize IP cores product family is focused on mobile and SOC technologies. The IP cores available in HDL form for synthesis to ASICs or optimized for Altera and Xilinx programmable logic devices. These cores are fully verified, and include a complete set of deliverables (synthesis scripts, testbenches, example designs, etc.) |
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Product |
Description |
Data sheet |
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UniPro IP Core |
The UNI100 soft IP core complies with the UniPro specification version 1.1 and glue-less connected to the MIPI D-PHY . The core implements the PHY Adapter, Data Link, Network, and Transport Layers as defined by the standard. The core is highly parameterized to allow the user selection of the best area to performance tradeoff for the system. The parameters are selected pre-synthesis (RTL) and unused options don’t cost silicon area. |
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SPI IP Core |
The Serial Peripheral Interface (SPI100) provides full-duplex, synchronous, digital, serial communication between master and slave, over a 4 wire bus. It can be connected to any peripheral supporting Motorola SPI synchronous serial interface or TI synchronous serial frame format. The SPI100 is AMBA AHB and/or APB slave for control, for status and for high bandwidth data transfer. The SPI100 can work with very fast serial bit clock over the interface in any rate up to eight times the frequency of the AHB or APB clock. The data flow can be CPU controlled by interrupts of various FIFO statuses or DMA controlled by dedicated DMA HW handshake. |
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Product |
Description |
Data sheet |
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AHB Matrix |
The AHB matrix soft IP core complies with the AMBA 2.0 specification. The AMBA Advanced High-performance Bus is tailored for high-performance, high-clock frequency system buses. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories, on chip peripheral and off-chip external peripheral functions. AHB is also specified to ensure ease of use in efficient design flow using synthesis and automated test techniques. |
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DMA Controller |
The DMAC100 is used to transfer large amounts of data between memories and peripherals using AHB/AXI buses in order to reduce CPU overhead for data transfers. The DMAC100 has one AHB Bus Slave interface for programming its internal registers and one or two bus master interfaces for data transfer. The DMAC100 has parameterized number of channels; each channel transfers data between one or two slaves (memory or peripheral). The direction, bus master, data width, transfer size, burst size and endiannity are configurable. Each bus master interface has its own channels requests arbiter. |
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Optimize for high speed |
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Low gate-count |
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Optimize for low power |
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Speed Vs. Power optimize |