ASIC Senior DFT Engineer
Job summary:
Our emerging UK branch is looking for excellent engineers to form out our backend group providing full RTL to GDSII flow. As a senior DFT engineer owning the complete DFT solutions in a chip design, you will have responsibilities spanning all aspects of chip design.
Description:
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Working with chip architecture team to define DFT specifications and define the chip test interface
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Developing and implementing DFT architecture
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Implementing DFT infrastructure
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Working with the validation team to verify DFT implementations and implement design changes
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Generating structural test vectors, analyzing and improving coverage
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Working with designers on STA, physical, power and logical issues
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Working with 3rd party IP’s vendor to integrate the provided design into the DFT infrastructure
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Working with test engineers to bring up test vectors on Silicon
Requirements:
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At least 5 years of DFT experience from VLSI companies - a must.
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Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
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Experience developing DFT specifications and driving DFT architecture and methods for designs
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Knowledge of industry standards DFT and design tools.
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Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
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Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues
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Experience with STA constraints development and analysis for DFT modes and SDF simulations
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Experienced in silicon bring-up, debug, and validation of DFT feature
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Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools.
Other locations:
Netanya, Israel, 1-2 travels per year may be required
Education:
BSEE is mandatory, MSEE - an advantage.
