ASIC Backend Design Engineer  

 

Job summary:

Our emerging UK branch is looking for excellent backend engineers with vast experience in chip design from RTL to GDSII full flow. In this position, you will be responsible, of large and complex blocks physical implementation.

 

Description:

  • Responsible for floor planning, physical synthesis and physical design closure of large complex designs at various processes including sub 40nm processes.

  • Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.

  • Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.

  • Resolve design and flow issues related to physical design, identify potential solutions

 

Requirements:

  • Minimum of 5 years hands-on experience in backend flow.

  • Experience with large SoC designs and complex blocks with frequencies more than 1GHz utilizing state of the art 28nm and below technologies.

  • Hands on experience in block level implementation including physical synthesis, placement, CTS, routing, and optimization using Synopsys ICC2/Cadence Innovus

  • Hands on experience in Synopsys DC/DCG.

  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.

  • Strong knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification

  • Well versed with timing constraints, STA and timing closure

  • Experience with low power design features and flows.

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now