Careers UK

Inomize UK is a daughter company of Inomize, a Research & Development company specializing in designing and delivering hardware solutions.
Since 2007, Inomize is a fast-growing company and the largest ASIC design firm in Israel. Our customers include leading international corporations and start-up companies from Israel, Europe, and North America.

Inomize UK, a new emerging R&D center, located in the Thames Valley, is currently operating two offices in  Bristol - Aztec West and Reading, and in Theale Arlington Business Park.

Our UK branch offers a challenging, creative, start-up environment that encourages excellence and personal initiatives.

If you are interested in joining our team, please send your CV to  jobs-uk@inomize.com.

 

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UK Career opportunities

 

Senior ASIC Backend Designer Engineer

 

Job summary:

Our emerging UK branch is looking for excellent backend engineers with vast experience in chip design from RTL to GDSII full flow. 

 

Description:

  • The role includes responsibility for floor planning, physical synthesis and physical verification of large complex designs Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.

  • As a leading member of physical/implementation design team, drive physical design and sub-micron methodologies and “best-known methods” to streamline physical design work, come up with guidelines and checklists and drive execution.

  • Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.

  • Resolve design and flow issues related to physical design, identify potential solutions

 

Requirements:

Key qualification:

  • Minimum 5 years hands-on experience in backend flow.

  • Experience with large SoC designs with frequencies more than 1GHz utilizing state of the art 28nm and below technologies.

  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.

  • Hands on experience in block level implementation including physical synthesis, P&R, CTS and optimization

  • Well versed with timing constraints, STA and timing closure and AC timing

  • Hands on experience with Physical Design Verification Flows - LVS/DRC/Antenna

  • Experience in EM/IR-Drop/Xtalk analysis 

  • Experience with low power design features and flows.

 

The candidate must have hands-on experience with the following Tools:

  • Floor planning and P&R tools:   Cadence Innovus and/or Synopsys ICC2

  • Synthesis Tools: Synopsys DC/DCG; Cadence Genus

  • Formal Verification: Synopsys Formality and Cadence LEC

  • Static Timing verification – Primetime

  • Physical Design Verification tools

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now

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STA and Timing Analysis Expert

 

Job summary:

Our merging UK branch is looking for excellent STA and timing constraint development engineers with vast experience. You will be taken part in the backend team as a frontend-backend focal point for timing and constraints development, working in advanced technologies and interacting closely both with RTL designers and Physical Designers. 

 

Description:

You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes. Deeply understanding constraints of 3rd party IP’s and integrating them into the toolchain for timing checks and timing signoff.

 

Requirements:

  • 3-5 years experience in STA that includes, but not limited to responsibility for timing and constraints

  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.

  • Extensive experience with Synopsys Prime Time.

  • Deep understanding of designs constraints development.

  • Familiarity with hierarchical design approach, top-down design, timing and physical convergence.

  • Experience with design synthesis and backend STA closure.

  • Good understanding of AC timing from specs to implementation.

  • Good understanding of DFT modes and their constraints.

  • Good communication and interaction with Design teams and PD teams.

  • Quick learning of flows and methods.

  • Good understanding of top level, RTL architecture implication on the physical implementation.

  • Hands on experience in ICC and DC is a must.

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now

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ASIC Senior DFT Engineer

 

Job summary:

Our emerging UK branch is looking for excellent engineers to form out our backend group providing full RTL to GDSII flow. As a senior DFT engineer owning the complete DFT solutions in a chip design, you will have responsibilities spanning all aspects of chip design.

 

Description:

  • Working with chip architecture team to define DFT specifications and define the chip test interface

  • Developing and implementing DFT architecture

  • Implementing DFT infrastructure

  • Working with the validation team to verify DFT implementations and implement design changes

  • Generating structural test vectors, analyzing and improving coverage

  • Working with designers on STA, physical, power and logical issues

  • Working with 3rd party IP’s vendor to integrate the provided design into the DFT infrastructure

  • Working with test engineers to bring up test vectors on Silicon

 

Requirements:

  • At least 5 years of DFT experience from VLSI companies - a must.

  • Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.

  • Experience developing DFT specifications and driving DFT architecture and methods for designs

  • Knowledge of industry standards DFT and design tools.

  • Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon

  • Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG/1500 related issues

  • Experience with STA constraints development and analysis for DFT modes and SDF simulations

  • Experienced in silicon bring-up, debug, and validation of DFT feature

  • Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools.

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now

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ASIC Backend Design Engineer  

 

Job summary:

Our emerging UK branch is looking for excellent backend engineers with vast experience in chip design from RTL to GDSII full flow. In this position, you will be responsible, of large and complex blocks physical implementation.

 

Description:

  • Responsible for floor planning, physical synthesis and physical design closure of large complex designs at various processes including sub 40nm processes.

  • Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.

  • Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.

  • Resolve design and flow issues related to physical design, identify potential solutions

 

Requirements:

  • Minimum of 5 years hands-on experience in backend flow.

  • Experience with large SoC designs and complex blocks with frequencies more than 1GHz utilizing state of the art 28nm and below technologies.

  • Hands on experience in block level implementation including physical synthesis, placement, CTS, routing, and optimization using Synopsys ICC2/Cadence Innovus

  • Hands on experience in Synopsys DC/DCG.

  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.

  • Strong knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification

  • Well versed with timing constraints, STA and timing closure

  • Experience with low power design features and flows.

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now

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Analog Team Lead Engineer

 

Job summary:

Our emerging UK branch is looking for excellent engineers to form out our analog group providing full Specifications to GDSII flow. We are looking for an Analog Designer with background in chip design from analog system specification to silicon Validation to become our UK analog team leader.

 

Description:

  • Working with analog group manager and customer on Specification of block or chip level definitions.  

  • Developing and implementing analog blocks and circuits from Spec. to schematic

  • Pre and post layout simulation and analysis of circuits

  • technical lead of complex block designs in various analog disciplines and techniques

  • responsibility for schedule and deliveries of analog team

  • Working with designers on stability , gain , performance , functional simulation of circuits

  • Working with 3rd party IP’s vendor to integrate the provided design into analog blocks

  • Reviewing layout and simulation results of the analog team members

 

Key qualifications:

  • At least 7 years hands on experience as an analog designer

  • At least 3 years of experience as an analog design team leader

  • Design experience with Analog Front End, op-amp, switch-cap filter, continuous time filter, reference/bias generation, LDO, Data conversion ADC and DAC subsystem, High speed I/O design, etc

  • Solid understanding of silicon design flow (design , verification, DRC, LVS , PEX and silicon validation)

  • Solid understanding of transistor device characteristics

  • Solid understanding of power, area and performance trade-off in mixed-signal designs

  • Experience with advanced CMOS processes (sub 40nm process) – an advantage

  • Solid understanding of packages and PCB modeling – an advantage

  • Solid understanding of test procedures, ESD , LU – an advantage

  • Solid understanding of high voltage design – an advantage

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSc. EE is mandatory, MSc. EE - advantage

 

Apply now

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Analog Engineer

 

Job summary:

Our emerging UK branch is looking for excellent engineers to form out our analog group providing full Specifications to GDSII flow. We are looking for an Analog Designer with background in chip design from analog system specification to silicon Validation to become our UK analog team leader.

 

Description:

  • Working with analog group manager and customer on Specification of block or chip level definitions.  

  • Developing and implementing analog blocks and circuits from Spec. to schematic

  • Pre and post layout simulation and analysis of circuits

  • technical lead of complex block designs in various analog disciplines and techniques 

 

Key qualifications:

  • At least 5 years hands on experience as an analog designer

  • Design experience with Analog Front End, op-amp, switch-cap filter, continuous time filter, reference/bias generation, LDO, Data conversion ADC and DAC subsystem, High speed I/O design, etc.

  • Solid understanding of silicon design flow (design , verification, DRC, LVS , PEX and silicon validation)

  • Solid understanding of transistor device characteristics

  • Solid understanding of power, area and performance trade-off in mixed-signal designs

  • Experience with advanced CMOS processes (sub 40nm process) – an advantage

  • Solid understanding of packages and PCB modeling – an advantage

  • Solid understanding of test procedures, ESD , LU – an advantage

  • Solid understanding of high voltage design – an advantage

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSc. EE is mandatory, MSc. EE - advantage

 

Apply now

 

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VLSI Digital Design Engineer

 

Description:

Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.

The role includes supporting design verification and backend to tape out of the full chip and supporting full chip integration and full chip related tasks – STA, verification and power analysis.

 

Requirements:

BSEE is required, MSEE is preferred.

5 and more years of experience in logic design using Verilog.

Experience with architecture, specs, documentation, coding in Verilog and debugging.

Knowledge of SoC, USB, DDR2/DDR3 and modem PHY designs – advantage.

 

Apply now

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