Careers NETANYA

Inomize is a Research & Development company specializing in designing and delivering hardware solutions.

Established in 2007, Inomize is a fast-growing company and the largest ASIC design firm in Israel. Our customers include leading international corporations and start-up companies from Israel, Europe, and North America.

 

At Inomize we offer a challenging, creative, and warm environment that encourages excellence and personal initiatives. We are extremely proud of our technological innovations and we strongly believe that our most valuable asset is our employees.

 

If you are interested in joining our team, please send your CV to  jobs@inomize.com

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Front-end positions

Backend positions

Mixed Signal positions

 

Senior Verification Engineer

 

Description:

This position includes hands-on SOC verification tests development for full chip, cluster, and block levels.

Planning and implementation of verification environments using automated tools - mainly System Verilog.

 

Requirements:

B.Sc. in Electrical or Computer Engineering or Computer Science.

Minimum 5 years of experience in SoC Verification.

Knowledge and experience in System Verilog or ‘e’ (Specman) languages.

Vast knowledge of verification flow (block level & full chip verification).

Familiarity with verification environments: VMM, OVM, UVM - an advantage. 

 

Apply now

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Verification Engineer

 

Description:

This position includes hands-on SOC verification tests development for full chip, cluster and block levels.

Planning and implementation of verification environments using automated tools - mainly System Verilog.

 

Requirements:

B.Sc. in Electrical or Computer Engineering or Computer Science.

2-5 years of experience in SoC Verification.

Knowledge and experience in System Verilog or ‘e’ (Specman) languages.

Vast knowledge of verification flow (block level & full chip verification).

Familiarity with verification environments: VMM, OVM, UVM - an advantage. 

 

Apply now

 

 

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Senior VLSI Engineer

 

Description:

Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.

The Responsibility also includes supporting design verification and backend to tape out of the full chip.

 

Requirements:

BSEE is required, MSEE is preferred.

Minimum 5 years of experience in logic design using Verilog.

Experience with architecture, specs, documentation, coding in Verilog and debugging.

Knowledge of USB, DDR2/DDR3 and modem PHY designs - an advantage.

Experience in full VLSI project flows - an advantage.

Knowledge in verification processes - an advantage.

 

Apply now

 

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VLSI Engineer

 

Description:

Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.

The Responsibility also includes supporting design verification and backend to tape out of the full chip.

 

Requirements:

BSEE is required, MSEE is preferred.

2-3 years of experience in logic design using Verilog.

Experience with architecture, specs, documentation, coding in Verilog and debugging.

Knowledge of USB, DDR2/DDR3 and modem PHY designs – advantage.

Experience in full VLSI project flows - an advantage.

Knowledge in verification processes - an advantage.

 

Apply now

 

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Senior VLSI Architect

 

Description:

Responsibility for defining an efficient hardware u-architecture to meet varies product requirements. Create and publish SoC u-architecture specification documents which provide the detailed requirements framework for ensuing SoC development.

Requirements:

BSEE is required, MSEE is preferred.

At least 6 years in VLSI design and architecture definition.

Experienced in designing multi-CPU platforms (DSPs and Microprocessors).

Experienced in Wireless MAC architecture or integration.

Experienced in performance/area/power estimation and optimization techniques.

Experienced in mixed-signals design- an advantage.

Extensive knowledge in Wi-Fi MAC and PHY architecture - an advantage.

Experienced in multimedia devices (Audio, Video, Graphics) architecture - an advantage.

Hands-on HW lab experience - an advantage.

Apply now

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VLSI Project Manager

 

Description:

Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.

The Responsibility also includes supporting design verification and backend to tape out of the full chip.

 

Requirements:

BSEE is required, MSEE is preferred.

At least 3 years experience in management of small-medium teams - a must. 

At least 5 years experience in logic design using Verilog - a must.

Experience with architecture, specs, documentation, coding in Verilog and debugging.

Knowledge of USB, DDR2/DDR3 and modem PHY designs - an advantage.

Experience in full VLSI project flows - an advantage.

Knowledge in verification processes - an advantage.

 

Apply now

 

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Verification Team Leader

 

Description:

Verification Team Leader with experience in leading verification team (~6 engineers).

 

Requirements:

B.Sc. in Electrical or Computer Engineering or Computer Science.

At least 3 years experience in technical managing of a small team (3-5 engineers) - a must.

Minimum 6 years of experience in verification flow - a must.

Knowledge of System-Verilog or Specman experience - a must. 

A clear understanding of constrained random verification process, functional coverage, code coverage and assertion methodology.

 

Apply now

 

 

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Junior Verification Engineer

 

Requirements:

B.Sc. in Electrical engineering or Computer engineering from a known university.

1+ years of experience in chip design OR Verification methodologies - Advantage.

Verilog OR System-Verilog OR E -Specman knowledge and experience- Advantage.

Knowledge of System-Verilog or Specman experience - a must. 

Understanding of constrained random verification process, functional coverage, and code coverage and assertion methodology- advantage.

Apply now

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Verification Technical Leader  - in Misgav area

 

For a major defense company in Misgav area.

This position includes hands-on verification of FPGA modules.

Planning and implementation of verification environments using System Verilog UVM methodology.

Technical guidance of a team of 2-3 junior engineers with potential to grow

 

Requirements:

B.Sc. in Electrical Engineering (from a known university).

Minimum 2 years of experience in System Verilog UVM/OVM Verification methodology.

Clear understanding of constrained random verification process, functional coverage, code coverage and assertion methodology

Experienced with architecture, specs, documentation and debugging.

Responsibility and dedication is a must

Familiarity with verification environments/languages: VMM, Specman, System C - advantage. 

 

Apply now

 

 

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FPGA Designer

 

Looking for an experienced FPGA Engineer, with strong capabilities throughout the entire FPGA development process.

 

Requirements:

Electrical Engineer degree from a leading university with More than 4 years of experience - Must.
Experience with Altera and Xilinx flows, including design entry, synthesis, place & route, timing constraints and closure - Must.

Experienced with architecture, specs, documentation, coding in VHDL/Verilog and debugging. 
Experienced with lab FPGA debug tools (like Chipscope / Signaltap) – Must

Knowledge of USB, DDR2/DDR3 and modem PHY designs – Advantage.
 

 

  Apply now

 

 

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Backend Team Leader

 

Description:

Backend Team Leader with a vast background in chip design from RTL to GDS.

 

Requirements:

BSEE is required, MSEE is preferred.

At least 2 years experience in leading a backend team.

At least 5 years hands-on experience in backend design.

Experience in RTL to GDS full flow, including Synthesis, DFT, Timing, constraints, multi-clock domains, low power design and high-frequency design methodologies, P&R, physical verification, etc.

 

 

Apply now

 

 

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Senior Backend Engineer

 

Description:

Backend Engineer with a vast background in chip design from RTL to GDS.

 

Requirements:

BSEE is required, MSEE is preferred.

At least 5 years experience in backend flow.

Experience with backend design for advanced CMOS processes (28nm and below).

Experienced in RTL to GDS full flow, including Synthesis, DFT, Timing, constraints, multi-clock domains, low power design and high-frequency design methodologies, P&R, physical verification, etc.

 

Apply now

 

 

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Senior DFT Engineer

 

Description:

As a DFT engineer owning the complete DFT solutions in a chip design, you will have responsibilities spanning all aspects of chip design.

 

Requirements:

BSEE is required, MSEE is preferred.

At least 6 years of DFT experience from VLSI companies - a must.

Strong knowledge in DFT techniques for high-performance SoC.

Experienced in industrial ATPG tools, Verilog simulation and scan debug tools.

Experienced in memory BIST and JTAG interfaces - an advantage.

Strong understanding of Logic Design, Verilog (RTL and GLV), verification and static timing analysis.

Experienced in silicon bring-up, debug, and validation of DFT features.

 

 

Apply now

 

 

 

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Senior CAD Engineer

Description:

This position includes definition and development of in-house tools for the R&D.

Drive technologies solutions and design automation for chip design engineering processes.

Involve the R&D methodologies to ensure optimal utilization and implementation.

 

Requirements:

B.Sc. / M.Sc. in Electrical Engineering or Computer Science - an advantage.

Experience in backend EDA tools acquaintance - a must.

Programming skills and knowledge of script languages: Perl/Shell/Python/TCL - a must.

Experience in C/C++ programming - an advantage.

Experience in software and design automation, understanding of data structures and algorithms.

Personal skills: Fast ramp up, quick learning, high motivation, independent.

 

Apply now

 

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Senior Analog Layout Engineer

 

Description:

Physical design (layout) for analog and digital blocks using EDA tools in cutting-edge silicon technologies.

 

Requirements:

Practical Engineer/B.tech/B.Sc. in Electrical or computer engineering- an advantage.

Experienced with layout editor tools: Virtuoso - a must, CDesigner, laker, genesis - an advantage.

Experienced with at least one of layout verification tools: Calibre, Hercules, ICV, PVS - a must.

Analog layout, IC, HSI, SerDes, RF, PLL, ADC, DAC, TX, RX, noise sensitive design, Band-Gap, voltage regulator - an advantage.

Strong understanding of analog design, floor-plan, cell level, block level, transistor level, matching, ESD, IR-drop, EM, noise

 

Apply now

 

 

 

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Analog Designer

 

Description:

Analog designer with block/circuit level know-how and experience.

 

Requirements:

BSEE is mandatory, MSEE/Ph.D. – an advantage.

At least 3-5 years hands-on experience in analog design.

Experience with advanced CMOS processes (45nm and below).

Experience with at least one analog design simulation tool (Hspice, Spectre, XA) is a MUST.

Experience with definition, design, simulation and layout review at block level for SOC.

Design experience with Analog Front End, op-amp, switch-cap filter, continuous time filter, reference or bias generation, LDO, DC-DC converters, data conversion ADC and DAC subsystem, High speed I/O design, etc.

Solid understanding of transistor device characteristics and manufacturing process impacts.

Solid understanding of power, area and performance trade-off in mixed-signal designs.

Familiarity with design modeling tools: Matlab or Verilog A- an advantage.

 

Apply now

 

 

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Analog Design Technical Leader 

 

Description:

Analog Designer with background in chip design from analog system specification to silicon verification 

In this position the technical lead will support the group manager on the following subjects:

  • Analog design lead experience.

  • Specification of block and chip level

  • Technical lead of a chip or block project

  • Environment and tools know how

  • Tools familiarity (virtuoso , DRC, LVS , parasitic extraction)

  • Package design experience

  • Process and manufacturing know how

  • Lab work experience

Requirements:

BSEE is mandatory, MSEE/PhD - advantage.

Minimum 5 years hands on experience in analog design.

Minimum 2 years’ experience in leading analog design team.

Solid understanding of silicon design flow (design , verification, DRC, LVS , PEX and silicon validation).

Solid understanding of transistor device characteristics.

Solid understanding of power, area and performance trade-off in mixed-signal designs.

Design experience with Analog Front End, op-amp, switch-cap filter, continuous time filter, reference/bias generation.

LDO, Data conversion ADC and DAC subsystem, High speed I/O design, etc.

Advantage:

Experience with advanced CMOS processes (45nm and below)

Solid understanding of packages and PCB modeling.

Solid understanding of test procedures, ESD , LU.

Solid understanding of high voltage design.

Apply now

 

 

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Static Timing Analysis Expert

Description:

STA Expert

 

Requirements:

BSEE is mandatory, MSEE - advantage.

At least 10 years of experience in STA

Experience with SoC practices such as multiple voltages and clock domains

Expertise in Prime-time - A must

Hands-on experience in ICC/DC - A must

Apply now

 

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Senior Digital Layout Engineer

Description:

Fab run-set Handling

 

Requirements:

Engineer/​BSEE is mandatory practical.

Must have at least 7 years of experience with LVS/DRC at chip/block level A.

Experience with ICC - A must.

Expertise with ICV or Calibre  - A must

​Apply now

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Junior Backend Engineer

 

Description:

We are looking for a brilliant student with fast learning abilities for our BE team. We are offering a variety of interesting practices in the implementation fields such as synthesis, Floor Plan, P&R, CTS, STA, DFT, physical verification sign-off. 

Requirements:

A 4th-year student.

B.Sc in Electrical Engineering or Computer Engineering from a known university.

Talented, innovator, and self-learner.

A team player with good interpersonal skills and problem-solving ability.

VLSI knowledge and experience - An advantage.

Experience in one or more of the following design fields is also an advantage: synthesis, timing analysis, power optimization, physical implementation.

Apply now

 

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Real-Time/Embedded Software Engineer

 

Position Overview:

You will be responsible to design, develop and implement complex software modules for embedded systems and SoC (System on Chip, ASIC). 

 

Requirements:

• B.Sc./B.A. in computer engineering or computer science or electrical engineering from a major university
• Proven experience with embedded software development
• Excellent C/C++ programming skills
• Ability to manage multiple tasks and priorities work to meet deadlines
• At least 5 years of relevant work experience.

 

Preferred Qualifications:

 Familiarity/Experience with one or more of the following will be an advantage:
o DSP programming
o Video streaming, image processing, computer vision
o Pre-silicon software design and EDA tools
o Knowledge with (one or more) architectures: ARM, ARC, MIPS, and Tensilica CPU’s
o Knowledge with (one or more) RTOS: ThreadX, FreeRTOS, MQX, etc.
o Embedded Linux (kernel)

 

Apply now

 

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Director,  Backend Group

 

We are looking for a talented Director to oversee our Backend Group. This candidate will be responsible for the full ASIC backend flow from RTL to GDS for highly complex SoCs designs. The position entails 

heading up all design flow cycles including synthesis, STA, Formal, block level PnR, floor-planning, clock and power distribution, power and noise analysis (EM / IR-Drop / Xtalk), layout verification (DRC / LVS). The candidate will interface with remote sites, contractors and conduct F2F discussion with customers. 

 

QUALIFICATIONS, SKILLS AND KNOWLEDGE REQUIREMENTS: 

  • B.Sc. in Electrical Engineering (Electronics) / Computer Engineering

  • 10+ years’ experience in Backend design of large scale SoC.

  • At least 3 years’ experience as a back-end team leader

  • Extensive experience with one of today`s available place & route tools (Synopsys / Cadence)

  • Experience with the hierarchical design approach, top-down design, timing and physical convergence

  • In-depth understanding of static-timing analysis

  • Extensive know-how in clock/power distribution and analysis, RC extraction

  • Experience with advanced CMOS process nodes (16nm/7nm)

  • Experience in integration of soft and hard IPs

  • Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration

  • Experience in scripting and programming using one or more of the following: Perl / TCL / Make;

  • Experience working in Unix environments with version control

  • Experience with Lynx flow - advantage

  • Knowledge in Verilog, DFT design – advantage

Apply now

 

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Senior Algorithm Engineer

Description

In this role you will be responsible for modeling and defining system level solutions for communication oriented blocks within mixed signals IC that incorporates full RX and TX paths. Modeling includes performance analysis, detail algorithm spec for implementation in HW and Fix-Point representation for bit exact verification.

 ​

Requirements

*BSc from a known university. MSc is an advantage.

*At least 6 years of experience in algorithm development for communication system.

*Experience in SW/HW projects that requires fixed point modeling  

*Modeling of Analog impairments - an advantage.

*Good mathematical background.

*Hands-on Matlab work.

Apply now

 

 

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