-
Is your prototype FPGA design ready and you want to move to mass production?
-
Are you seeking assistance in migrating from FPGA design to a production ready ASIC?
-
Did you encounter an EOL (End of Life) product (either ASIC or FPGA) which your design is based on?
-
Do you need to replacement and it hard to find?
Developing an ASIC is a complex process which requires many skills and experience. Selecting a partner for an ASIC manufacturing is a critical decision in a company course of life, since some mistakes may cost many thousands of dollars to remanufacture.
Why migrating from FPGA to an ASIC?
Reducing BOM cost (see a simple example below), reducing power consumption, reducing physical solution size, increasing performance, controlling your product future, implementing relevant components in the product, implementing more than one component into a single ASIC solution.
Other reasons for ASIC implementations may be ASIC end of life (ASIC to ASIC) while keeping the same pin location, implementing several ASICs to a single ASIC, migrating old technology ASIC to a new technology ASIC and many more.
A simple BOM cost reduction calculation:
-
FPGA cost- ~$50
-
Amount of systems with FPGA – 100,000 units
-
Total FPGA cost: $50 * 100,000 = $5,000,000
______________________________________________ -
Mass production ASIC Cost - ~3$
-
Amount of systems with ASIC – 100,000 units
-
Total ASIC cost: $3 * 100,000 = $300,000
-
NRE cost (design, verification and production cost): even with a cost of $3,000,000, the total cost is much less than using FPGA
Harness Inomize’s vast experience of many years in implementing ASICs and designing complex FPGAs to your needs and get results in a different level of quality. Inomize is a partner for life from requirements stage all the way to your working ASIC or FPGA.
Customer project required information:
-
Target application and market
-
Block diagram
-
Specification or datasheet
-
FPGA utilization report
-
Memory list and type
-
Clock tree schematics
-
Package and IO requirements
-
Testability requirements (scan, mBIST, JTAG, Lbist ect.)
-
Qualification requirements
-
Other special requirements
-
Analog IP’s like ADC, DAC, PLL IO’s, SerDes etc. and 3rd party IP’s like PLL, IO’s, SerDes, LP/DDRx, CPU/DSP etc.
-
High speed interface and 3rd party IP’s like, LP/DDRx, CPU/DSP USB etc
-
Target TO (Tape-out) date
-
Quantities YoY (year over year)
-
First time user requires/university name and address for TSMC 3-Way-NDA
Special Offer
Inomize offers a wide range of ASIC design services. Please contact us for more information.