IP

 

Compression/De-Compression

 

GZIP/GUNZIP compression/decompression is fast becoming the industry standard for lossless data compression.

GZIP is a very common compression in many applications as it significantly reduces the size of data while maintaining the original files unchanged.

(This is in contrast to graphic applications, which use lossy compression methods such as Jpeg and Mpeg ).

 

GZIP/GUNZIP applications include:

 

  • Data storage backup devices,

  • HTTP web servers,

  • Point to point or point to multi-point communications.

 

Read more:

 

 IP - GZIP HW Accelerator

Highlights:

  • Static Huffman compression core  history buffer size = 256

  • Standard cells implementation - without ROM or SRAM

Main Features:

  • Synthesizable Verilog soft core suitable for FPGA and ASIC implementations.

  • RFC1951 (Deflate)  and RFC1952 (GZIP) compliance

  • Fully Pipelined implementation for maximum performance

  • Multi-threaded: files can be compressed in parts, by performing concurrent compression of several files by several threads.

  • Streaming data interface which enables maximum performance and integration flexibility.

Performance:

  • Throughput: 1 input byte per clock cycle.

  • Very small latency: 20 clock cycles. 

  • No delay between subsequent files.

  • Compression speed (single core):

    • ASIC (TSMC 40nm lp): 800MHz gives a sustained compression speed of 6.5 Gbps.

    • FPGA: 480MHz on Xilinx Kintex UltraScale+ gives a sustained compression speed of 4 Gbps.

    • More than 100Gbps with multiple cores instantiation.

  • More than 100Gbps using parallel instantiation of several cores. 

 

 

 

 

 

 

Compression ratio:

Using the “Canterbury Corpus” industry standard benchmark:

The average compression ratio is 45% (1/2.2)

Resource Utilization:

  • FPGA: 1071 LUTs + 1 RAMB 18 of Xilinx Kintex UltraScale+

  • ASIC: 58000 logic gates (only standard cells)/

 

Deliverables:

  • Synthesizable Verilog HDL

  • Verilog test-bench and test-suite (with Perl script)

  • Available option – C model

  • Available option – FPGA demo

 

Block Diagrams:

 

 

 

 

 

 

 

 

 

 

 IP - GUZIP HW Accelerator

 

Highlights:

  • Static Huffman Decompression core with history buffer = 256

  • Standard cells implementation - without any ROM or SRAM

Main Features:

  • Synthesizable Verilog soft core suitable for FPGA and ASIC implementations.

  • RFC1951 (Deflate)  and RFC1952 (GZIP) compliance

  • Fully Pipelined implementation for maximum performance

  • Streaming data interface which enables maximum performance and integration flexibility.

Performance:

  • Throughput of 1 output byte per clock cycle (decompressed data).

  • Very small latency:36 clock cycles.

  • No delay between subsequent files.

  • Compression speed (single core):

    • ASIC (TSMC 40nm lp): 640MHz gives a sustained compression speed of 5.0 Gbps.

    • FPGA: 660MHz on Xilinx Kintex UltraScale+ gives a sustained compression speed of 5.2 Gbps.

  • More than 100 Gbps using parallel instantiation of several cores.

 

Resource Utilization:

  • FPGA: 3483 LUTs + 2 RAMB18 of Xilinx Kintex UltraScale+

  • ASIC: 52260 logic gates (Standard cells only)

 

Deliverables:

  • Synthesizable Verilog HDL

  • Verilog test-bench and test-suite (with Perl script)

  • Available option – FPGA demo

 

Block Diagrams: