Senior ASIC Backend Designer Engineer
Job summary:
Our emerging UK branch is looking for excellent backend engineers with a vast experience in chip design from RTL to GDSII full flow.
Description:
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The role includes responsibility for floor planning, physical synthesis and physical verification of large complex designs Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
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As a leading member of physical/implementation design team, drive physical design and sub-micron methodologies and “best-known methods” to streamline physical design work, come up with guidelines and checklists and drive execution.
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Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.
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Resolve design and flow issues related to physical design, identify potential solutions
Requirements:
Key qualification:
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Minimum 5 years hands-on experience in backend flow.
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Experience with large SoC designs with frequencies more than 1GHz utilizing state of the art 28nm and below technologies.
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Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.
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Hands on experience in block level implementation including physical synthesis, P&R, CTS and optimization
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Well versed with timing constraints, STA and timing closure and AC timing
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Hands on experience with Physical Design Verification Flows - LVS/DRC/Antenna
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Experience in EM/IR-Drop/Xtalk analysis
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Experience with low power design features and flows.
The candidate must have hands-on experience with the following Tools:
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Floor planning and P&R tools: Cadence Innovus and/or Synopsys ICC2
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Synthesis Tools: Synopsys DC/DCG; Cadence Genus
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Formal Verification: Synopsys Formality and Cadence LEC
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Static Timing verification – Primetime
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Physical Design Verification tools
Other locations:
Netanya, Israel, 1-2 travels per year may be required
Education:
BSEE is mandatory, MSEE - an advantage.
