Senior DFT Engineer
As a DFT engineer owning the complete DFT solutions in a chip design, you will have responsibilities spanning all aspects of chip design.
BSEE is required, MSEE is preferred.
At least 6 years of DFT experience from VLSI companies - a must.
Strong knowledge in DFT techniques for high-performance SoC.
Experienced in industrial ATPG tools, Verilog simulation and scan debug tools.
Experienced in memory BIST and JTAG interfaces - an advantage.
Strong understanding of Logic Design, Verilog (RTL and GLV), verification and static timing analysis.
Experienced in silicon bring-up, debug, and validation of DFT features.