Senior Verification Engineer

 

Description:

This position includes hands-on SOC verification tests development for full chip, cluster and block levels.

Planning and implementation of verification environments using automated tools - mainly System Verilog.

 

Requirements:

B.Sc. in Electrical or Computer Engineering or Computer Science.

Minimum 5 years of experience in SoC Verification.

Knowledge and experience in System Verilog or ‘e’ (Specman) languages.

Vast knowledge of verification flow (block level & full chip verification).

Familiarity with verification environments: VMM, OVM, UVM - an advantage. 

 

Apply now

Visit

Headquaters-Israel:
6 Meir Ariel St. 
Netanya 

8 Hartom St. ,Jerusalem 

United Kingdom office

London - EC1M 6BB

Reading - RG7 4TY

Swindon - SN5 6QR

Call

Tel:   +972 72-277-5400

Fax:  +972-72-277-5401

   Inomize Ltd.

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