Senior Verification Engineer

 

Description:

This position includes hands-on SOC verification tests development for full chip, cluster and block levels.

Planning and implementation of verification environments using automated tools - mainly System Verilog.

 

Requirements:

B.Sc. in Electrical or Computer Engineering or Computer Science.

Minimum 5 years of experience in SoC Verification.

Knowledge and experience in System Verilog or ‘e’ (Specman) languages.

Vast knowledge of verification flow (block level & full chip verification).

Familiarity with verification environments: VMM, OVM, UVM - an advantage. 

 

Apply now