STA and Timing Analysis Expert

 

Job summary:

Our merging UK branch is looking for excellent STA and timing constraint development engineers with vast experience. You will be taken part in the backend team as a frontend-backend focal point for timing and constraints development, working in advanced technologies and interacting closely both with RTL designers and Physical Designers. 

 

Description:

You will be responsible for constraints and timing checkups development, including their delivery for synthesis, PnR and signoff STA. Working in parallel on blocks and chip level STA modes. Deeply understanding constraints of 3rd party IP’s and integrating them into the toolchain for timing checks and timing signoff.

 

Requirements:

  • 3-5 years experience in STA that includes, but not limited to responsibility for timing and constraints

  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.

  • Extensive experience with Synopsys Prime Time.

  • Deep understanding of designs constraints development.

  • Familiarity with hierarchical design approach, top-down design, timing and physical convergence.

  • Experience with design synthesis and backend STA closure.

  • Good understanding of AC timing from specs to implementation.

  • Good understanding of DFT modes and their constraints.

  • Good communication and interaction with Design teams and PD teams.

  • Quick learning of flows and methods.

  • Good understanding of top level, RTL architecture implication on the physical implementation.

  • Hands on experience in ICC and DC is a must.

 

Other locations:

Netanya, Israel, 1-2 travels per year may be required

 

Education: 

BSEE is mandatory, MSEE - an advantage.

 

Apply now