VLSI Digital Design Engineer



Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.

The role includes supporting design verification and backend to tape out of the full chip and supporting full chip integration and full chip related tasks – STA, verification and power analysis.



BSEE is required, MSEE is preferred.

5 and more years of experience in logic design using Verilog.

Experience with architecture, specs, documentation, coding in Verilog and debugging.

Knowledge of SoC, USB, DDR2/DDR3 and modem PHY designs – advantage.


Apply now


6 Meir Ariel St. 

8 Hartom St. ,Jerusalem 

United Kingdom office

London - EC1M 6BB

Reading - RG7 4TY

Swindon - SN5 6QR


Tel:   +972 72-277-5400

Fax:  +972-72-277-5401

   Inomize Ltd.

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