Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.
The Responsibility also includes supporting design verification and backend to tape out of the full chip.
BSEE is required, MSEE is preferred.
2-3 years of experience in logic design using Verilog.
Experience with architecture, specs, documentation, coding in Verilog and debugging.
Knowledge of USB, DDR2/DDR3 and modem PHY designs – advantage.
Experience in full VLSI project flows - an advantage.
Knowledge in verification processes - an advantage.