VLSI Project Manager
Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.
The Responsibility also includes supporting design verification and backend to tape out of the full chip.
BSEE is required, MSEE is preferred.
At least 3 years experience in management of small-medium teams - a must.
At least 5 years experience in logic design using Verilog - a must.
Experience with architecture, specs, documentation, coding in Verilog and debugging.
Knowledge of USB, DDR2/DDR3 and modem PHY designs - an advantage.
Experience in full VLSI project flows - an advantage.
Knowledge in verification processes - an advantage.